Design of Low Power Column Bypass Multiplier using FPGA and Implementation Using FIR Filter.

Design of area, high speed and power efficient data path logic systems in the low power VLSI circuits has been identified as vital technology in the in the DSP computations and signal processing applications like FIR,IIR filters. Since multipliers consume most of the power in DSP computations it is very important to develop new low-power multipliers for DSP computations. The switching activity of the multiplier depends on the input bit-coefficient, if the coefficient bits are zero the corresponding rows or columns need not to be activated. By inserting more number of zeros in the multiplicand using booth recoding unit we can reduce the switching activity by shutting down the idle part of the circuit and thereby reducing the power dissipation, based on this concept we presents low power column bypass multiplier and verifies the result using FIR filter.