Title of article
Parameter Optimization Performance Analysis of 4-Bit CMOS Layout for Adder
Author/Authors
Nimade، Prof. Sandip نويسنده TIT College, Bhopal , , Shukla، Amrita نويسنده Technocrats Institute of Science and Technology, Bhopal , , Gupta، Vikas نويسنده TIT Bhopal ,
Issue Information
روزنامه با شماره پیاپی سال 2013
Pages
4
From page
111
To page
114
Abstract
This paper we design 4-bit CMOS layout for 4-bit full adder with the help of half adder and other logic gates. In this paper we calculate power dissipation of gates and modules which we used in designing and also calculate the no. of transistors which were used in designing of gates. The result of simulation of adder layout is in Microwind2.
Journal title
International Journal of Engineering Innovations and Research
Serial Year
2013
Journal title
International Journal of Engineering Innovations and Research
Record number
2003329
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