Production testing issues for ASICs for high energy physics

Many high-energy physics experiments require a large number of channels in a small volume. The use of custom or Application Specific Integrated Circuits (ASICs) in the front ends is very popular and in many cases an absolute necessity. The tools to design ASICs are readily available and wafers can be processed at moderate costs. However, very few, if any, vendors will provide tested die or chips at a reasonable cost in the low quantities (few thousand to few tens of thousands) that most experiments require. This talk will discuss the cost of testing vs. not testing of ASICs as well as ASIC testing strategies and solutions for relatively small quantities of ASICs. Specifics of the solution used by the KTeV experiment at Fermilab and the low-cost test system developed for this need will be discussed.