Title of article
A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment
Author/Authors
De Robertis، نويسنده , , G and Loddo، نويسنده , , F and Ranieri، نويسنده , , A، نويسنده ,
Pages
7
From page
394
To page
400
Abstract
The design of a high speed Sorting Processor ASIC is presented. It was designed in BiCMOS 0.8 μm technology and its aim is to reorder and provide the four highest words among eight input words, in decreasing order. This chip is the main component of the sorting tree of the Trigger Muon System of the CMS experiment.
Journal title
Astroparticle Physics
Record number
2010300
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