Author/Authors :
Ushiroda، نويسنده , , Y. and Mohapatra، نويسنده , , Anatoly A. and Sakamoto، نويسنده , , H. K. Sakai، نويسنده , , Y. and Nakao، نويسنده , , M. and An، نويسنده , , Q. and Wang، نويسنده , , Y.F.، نويسنده ,
Abstract :
In this paper, we describe the design and development of the central trigger system (GDL) for the BELLE detector at the KEK B-factory. The GDL consists of four types of single width 6U VME modules (ITD, FTD, PSNM and TMD) which are designed using the programmable logic techniques of Xilinx FPGA and CPLD. Individual and combined performance tests of these modules are done and it is confirmed that the GDL functions as expected.
