Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip

A new pixel readout prototype has been developed at CERN for high-energy physics applications. This full mixed mode circuit has been implemented in a commercial 0.5 μm CMOS technology. Its radiation tolerance has been enhanced by designing all NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The technique is explained and its effectiveness demonstrated on various irradiation measurements on individual transistors and on the prototype. Circuit performance started to degrade only after a total dose of 600 krad–1.7 Mrad depending on the type of radiation. 10 keV X-rays, 60Co gamma-rays, 6.5 MeV protons, and minimum ionizing particles were used. Implications of this layout approach on the circuit design and perspectives for even deeper submicron technologies are discussed.