Study, Implementation and Comparison of Different Array Multipliers using Modified Shannon Based Adder Cell.

For a longer battery life a device with less power consumption is desired. Multiplier is the basic component of mostly digital systems so a multiplier with low power dissipation and less area is desirable. In this paper Carry save array (CSA) array multiplier is designed using Modified Shannon based adder cell and compared with other existing work in terms of power dissipation. The parameters are analyzed using BSIM4 model at 90nm deep submicron technology. The schematic is developed using DSCH 3.1 CAD tool and layout is generated using Microwind 3.1 CAD tool. The Modified Shannon based adder cell is optimized using transistor sizing technique. The CSA multiplier shows better performance with optimized modified Shannon based adder cell.