Analysis of Settling Time for Low Power CMOS Multistage Operational Amplifiers.

Design procedure for multistage CMOS op-amp with features of fast settling and low power consumption is present in this paper. This method is focused on optimum compensation by means of proper placement of poles and zero. Single-stage cascode amplifier is no longer suitable in low-voltage designs. So that Multi-stage amplifiers are required with advance in technologies. To reduce the settling time and find the high gain in multi-stage Op-Amp, main aim is minimum mos used in this technology. Nested Miller compensation nulling-resistor technique is used. Simulations on a circuit implemented in a 0.35-?m technology closely to the results expected. Three stage op-amp circuits are simulated by Tanner tool. The results obtained by the circuit simulation are 163 nsec (Settling Time), 90dB (Gain), 9.3 V/µs (Slew Rate) and 11 MHz (Unity Gain Frequency).