Hardware Implementation of AES.

The Advanced Encryption Standard algorithm can be efficiently programmed in software and implemented in hardware. Field Programmable Gate Array (FPGA) devices are considered as efficient and cost effective solution for hardware. This research is in context to efficient hardware implementation of AES algorithm with language platform as VHDL (Very High Speed Integrated Circuit Hardware Description language). This research is in context to efficient hardware implementation of AES algorithm with 128-192-256 key all in one module with language platform as VHDL (Very High Speed Integrated Circuit Hardware Description language). The software part has been created, processed and simulated through Xilinx ISE 9.2. A compact design approach has been chosen to implement the algorithm with minimal hardware. As for hardware, Spartan 3AN family device (XC3S700A) device is used.