Discrete Time Sigma-Delta Modulator with the Objective of Power Consumption Reduction with 130 um Technology

In this paper a mono-loop discrete time sigma-delta modulator of order 2 is designed and implemented. The major aim of the design is to decrease the power consumption. To attain this goal this paper attempts to optimize the high power characteristic of the OTA modulators. Using an appropriate design and taking the power of biasing sources into account, the amplifier expends 1 mw for operation. At first, this modulator is simulated using MATLAB software as a system which encounters various conditions. The blocks of this modulator, in circuit level, are simulated with ADS software. The operational frequency of this modulator is 12 KHz whose ultra sampling rate is 256 for SNR?85dB.