Designing a 64-Point FFT/IFFT Processor for Implementation of OFDM in High Speed WLAN Applications

In this report a methodology is presented for design of a special 32-bit 64-point processor to implement the OFDM in local wireless networks with IEEE standard 800.11a. In this FFT/IFFT, instead of direct approach, the shifter and adder is used for multiplier; thereby, it yields a major reduction in power area. In this processor a memory bank with the number of elements N=algorithmʹ base is considered. On this basis, the callback for digits is performed just in one stage as well as the access time to the memory is reduced.