Timing Simulation of Metastability and Soft Errors in CMOS Interface Sequential Circuits.

Metastability is a widespread phenomenon and errors may occur in any synchronous circuit where an input signal can change randomly with respect to a reference signal. The reference signal may be either a voltage based reference, such as a bias voltage, or a time based reference, such as a clock signal. Circuits in which metastability can occur include analog-to-digital converters, memories, time digitizers, and bus controllers etc.. During the sampling phase, flip-flop accepts input data (D) at an arbitrary time and produces output (Q) that aligns to the clock signal (CLK). It has an aperture defined by the setup and hold time around the rising/falling edge of the clock. If the data transitions outside of the aperture, Q (Q_Stable) should equal D. If the data changes during the aperture, the value of Q (Q_Metastable) may enter the metastable region resulting in a long time for Q to resolve to a stable value and therefore an unpredictable final value of Q. Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either ʹ1ʹ or ʹ0ʹ. This whole process is known as metastability.