Differential non-linearity compensation in ADCs employing charge redistribution in an array of binary weighted capacitors

Differential non-linearity (DNL) compensation in an analog-to-digital converter (ADC) is discussed. The successive approximation ADC under study employs charge redistribution in an array of binary weighted capacitors. The method of DNL compensation is supposed to be implemented in the ADC destined for the tracker readout of the CMS detector at LHC. The parameters of the DNL compensation technique are treated with the constructed simulator built in the Mathematica programming environment.