The pixel detector readout ASIC for the MicroVertex Detector of the PANDA experiment

The silicon pixel detector of the PANDA experiment is characterized by both high track density and the absence of a hardware trigger signal, thus leading to a huge amount of data to be acquired and transmitted to the DAQ. In order to cope with such challenging requirements, an ASIC based custom solution for the electronic readout has been chosen. The ASIC, named ToPiX, will provide the time position of each hit and a measure of the charge released with the Time over Threshold (ToT) technique. A reduced scale prototype in a CMOS 0.13 μ m technology has been designed and tested. The prototype includes four columns made of 128 pixel cells, four columns of 32 cells and the end of column readout with a 32 cells deep FIFO for each double column. Each cell embeds a charge amplifier with constant current feedback capacitor discharge, a comparator with per cell adjustable threshold, 12-bits leading and trailing edge register for time and ToT measurement and an 8 bits configuration register. All the readout logic has been SEU-hardened by design using either Hamming encoding or triple modular redundancy. The chip has been tested both electrically via a test pulse input and connected to a detector in a beam test.