Noise characterization of a 0.25 μm CMOS technology for the LHC experiments

After having reviewed the main noise sources in an MOS transistor the paper presents results about the noise performance of a 0.25 μm CMOS technology which is being extensively used to design radiation tolerant ASICs for the LHC experiments (the Large Hadron Collider at present under construction at CERN). The 1/f and white noise are studied for n- and p-channel devices with five different gate lengths, in weak, moderate and strong inversion and for different drain to source and bulk to source biases. The noise degradation is measured after irradiation with 10 keV X-rays and after annealing. The results are commented in view of the use of these transistors in low-noise front-end circuits.