Readout architecture of the CMS pixel detector

In this paper we describe the readout architecture of the CMS pixel chip. In column drain architecture the complex tasks of data buffering and trigger verification are performed in the circuit periphery. This allows to use a rather simple pixel unit cell which requires only a small number of transistors. The column periphery logic is designed for readout and trigger rates expected for full LHC luminosity. At LHC the high particle flux can create single event upsets in the readout chips. At small radii the upsets of logic cells could severely affect the performance of the pixel detector readout. We have therefore performed a measurement of the upset rate at the PSI pion beam and describe the consequences for the design of the readout chip.