High efficiency readout circuits for large matrices of pixels

In future collider experiments the increasing luminosity and center of mass energy are rising challenges in the research field of tracking systems where it is crucial to have very fast sensors with efficient readout in order to sustain the high particle flux. In this context we propose a high-efficiency digital readout architecture for large binary pixel matrices that is meant to cope with high hit-rates, up to 100 MHz/cm2, foreseen in the innermost tracker layer of the new generation particle accelerators. We modelled and designed several readout circuits to be integrated in the periphery of hybrid detectors. In this work we focus on a particular solution, to be interconnected to a 200 × 256 ‐ pixel matrix covering an area of 1.3 cm2. The hits are latched at pixel level, and the matrix provides a digital interface to the peripheral digital readout. The architecture is highly paralleled in order to reduce the pixels dead time introduced by readout which can be operated in data-push or triggered mode. In addition, a cluster compression algorithm, exploiting also the time sorted hit extraction, has been developed to reduce the output bandwidth. The architecture has been modelled in a hardware description language, to be synthesized in a net-list of foundry standard-cells. A Monte Carlo hit generator has been attached to simulations to evaluate the readout efficiency, both in data-push and triggered working mode. Simulation results will be presented, pointing out beside the efficiency results, the benefits introduced by the compression algorithm.