Author/Authors :
Chang، نويسنده , , M.C. and Gao، نويسنده , , Z.W. and Guo، نويسنده , , Y.N. and Kawasaki، نويسنده , , T. and Ueno، نويسنده , , K. and Velikzhanin، نويسنده , , Y.S.، نويسنده ,
Abstract :
We have developed a Trigger Timing Module (TTM2) for the control and readout electronics (CORE) of the upgraded Silicon Vertex Detector (SVD2) for use in the BELLE experiment. Eleven Trigger Timing Modules located at one VME-crate provide timing and strobe signals for the SVD2 CORE electronics and make communication between SVD2 and Global Decision Logic of the BELLE data acquisition system. The main motivation to make a new TTM design is to avoid glitches.
Keywords :
Waveform , VME , Belle , FPGA , RAM