Design and fabrication of a 0.25 μm Rad-Hard ASIC for ALICE ITS data acquisition system

This paper explains the design and the realization of a digital Rad-Hard chip. The design is a part of the Large Hadron Collider (LHC), A Large Ion Collider Experiment (ALICE) at CERN. The chip has been designed in VHDL-Verilog language and implemented in 0.25 μm CMOS 3-metal Rad-Hard CERN library. It is composed of 10 kgates, 84 I/O pads out of the 100 total pads, it is clocked at 40 MHz, it is pad-limited and the whole die area is 4×4 mm2. The chip has been tested over 20 packaged samples and it has been proved that 12 out of 20 chips work well.