Novel low-temperature processing of low noise SDDs with on-detector electronics

We have developed a fabrication process (SMART700° process) for monolithic integration of p-channel JFETs and silicon detectors. Processing steps of the SMART700° do not exceed 700°C. The integrated p-JFET has a minimum gate length of 1 μm. A relatively large width can be chosen to achieve a reasonable transconductance, while the JFET capacitance still matches the small capacitance of a detector. The feedback capacitor was also realized on-chip as a double-metal capacitor. In this paper we describe DC and noise characteristics of a silicon drift detector (SDD) with a p-JFET (W/L=100/1) and a feedback capacitor integrated in the read-out anode (smart-SDD). The device has a transconductance of 1–3 mS, a top gate capacitance of ∼140 fF and a low leakage current (<10 nA/cm2 at room temperature). The smart-SDD with an active area of 3.8 mm2 has reached an energy resolution of ∼50 rms electrons at a temperature of 213 K. This relatively poor energy resolution is due to generation-recombination noise caused by defects produced by a deep n-implantation. Rapid thermal annealing (RTA) and excimer laser annealing (ELA) techniques are experimented to remove the implantation damage. The noise of p-JFETs annealed with RTA and ELA is also presented.