Author/Authors :
Ashmanskas، نويسنده , , Bill and Barchiesi، نويسنده , , A. and Bardi، نويسنده , , A. and Bari، نويسنده , , M. and Baumgart، نويسنده , , M. and Belforte، نويسنده , , S. and Berryhill، نويسنده , , J. and Bogdan، نويسنده , , M. and Carosi، نويسنده , , R. and Cerri، نويسنده , , A. and Chlachidze، نويسنده , , G. and Culbertson، نويسنده , , R. and DellʹOrso، نويسنده , , M. and Donati، نويسنده , , S. and Fiori، نويسنده , , I. and Frisch، نويسنده ,
Abstract :
The Collider Detector at Fermilab (CDF) experimentʹs Silicon Vertex Trigger (SVT) is a system of 150 custom 9U VME boards that reconstructs axial tracks in the CDF silicon strip detector in a 15 μs pipeline. SVTʹs 35 μm impact parameter resolution enables CDFʹs Level 2 trigger to distinguish primary and secondary particles, and hence to collect large samples of hadronic bottom and charm decays. We review some of SVTʹs key design features. Speed is achieved with custom VLSI pattern recognition, linearized track fitting, pipelining, and parallel processing. Testing and reliability are aided by built-in logic state analysis and test-data sourcing at each boardʹs input and output, a common interboard data link, and a universal “Merger” board for data fan-in/fan-out. Speed and adaptability are enhanced by use of modern FPGAs.
Keywords :
trigger , DATA ACQUISITION , Real time pattern recognition , Position-sensitive detectors , Tracking
