Analog front ends for highly segmented detectors

The evolution of analog front end ASICs is being driven by the increasing interest in fine-grained detectors and by rapid reduction in transistor feature size. Existing and proposed 2D pad and pixel detectors are moving towards higher segmentation in order to increase position resolution and/or signal-to-noise ratio. As pixel density increases above 104 pixels/cm2, the power dissipation of the front-end ASIC becomes a serious constraint. We discuss the power-constrained noise optimization of ASIC front ends in scaled CMOS technology.