Author/Authors :
S. and Imbergamo، نويسنده , , E. and Nappi، نويسنده , , A. and Papi، نويسنده , , A. and Riccini، نويسنده , , A. and Valdata-Nappi، نويسنده , , M.، نويسنده ,
Abstract :
We present a method for the evaluation, at the first level of trigger, of logical conditions with high time resolution, using the digitized times of fast signals in high rate experiments. We describe a dead-time-less implementation of this method on a commercial FPGA. The method offers an excellent solution to the problem of including veto conditions in the first level of trigger for experiments on rare kaon decays.
Keywords :
trigger , FPGA , Coincidences , digital systems
