Development of a triple well CMOS MAPS device with in-pixel signal processing and sparsified readout capabilities

The SLIM5 collaboration has designed, fabricated and tested several prototypes of CMOS Monolithic Active Pixel Sensors (MAPS). The key feature of these devices, with respect to traditional MAPS is to include, at the pixel level, charge amplification and shaping and a first sparsification structure that interfaces with on-chip digital readout circuits. Via the 3-well option of the applied 0.13 μ m ST-Microelectronics CMOS technology each pixel includes a charge preamplifier, a shaper, a discriminator, an output latch, while retaining a fill factor of the sensitive area close to 90%. The last device of the family was submitted on Q4 2006 and the tests are ongoing. On this sensor, an on-chip, off-pixel digital readout block (streamout data sparsification) was added to implement, to control and to readout a test matrix built up of 4 × 4 pixels. It is aimed at proposing solutions that will overcome the readout speed limit of future large-matrix MAPS chips.