Wafer bonding and H-implantation mechanisms involved in the Smart-cut® technology

Silicon-on-insulator (SOI) material, mainly known for high-temperature and radiation hard niche applications, is now increasingly used for low power and low voltage devices. The new Smart-Cut® SOI process, which appears as a good candidate to reach ULSI criteria, is described. Effects of physical phenomena, such as H-implantation, stiffer bonding quality and wafer cleaning, are presented. Formation mechanisms of the various bonding defects are discussed and related to particles trapped at the interface. The understanding of these mechanisms enabled SOI wafers to be obtained without any macroscopic defect. Thermal dependence of the interface quality revealed by a selective chemical etching is presented. The Smart-Cut® process leads to the formation of an SOI structure with a high top silicon thickness homogeneity and a surface microroughness comparable with that of the silicon substrate.