Current trends in silicon defect technology

Defects in silicon crystals have been of great scientific and technological interest since before the earliest days of the silicon transistor. Recently much attention has been focussed on crystal originated pits (COPs) on the polished surface of the wafer. These defects have been shown to degrade gate oxide quality. Although it is thought that the effect of COPs on thinner gate oxides in future generations will not be so severe, considerable effort has been directed toward reducing their density in the grown crystal. This can be done by controlling the thermal gradient and pull rate during crystal growth. Other techniques for reducing the incidence of COPs include epitaxial deposition or high-temperature hydrogen annealing. Another class of defects that evokes considerable interest is surface metals. These tend to decorate stacking faults and other defects in the crystal and degrade the device characteristics. The degree of degradation may increase or decrease as the line width shrinks depending on the processing circumstances. Stress induced during high temperature processing can lead to the formation of slip in the wafer. For large diameter wafers (≥300 mm), sag due to gravitational forces must be taken into account in addition to thermal stresses. Other stresses induced during device processing can propagate dislocations and generate other defects that are also detrimental to device performance. Hydrogen and oxygen are two impurities that impact material performance in multiple ways, and their control continues to be of prime importance in silicon technology.