Compared rapid thermal annealing procedures of InP

In the context of the optimization of InP Rapid Thermal Annealing (RTA), two methods were analyzed and compared. In the first one, the sample is sandwiched between two silicon wafers. It is enclosed in a graphite cell in the second one. Deep level transient spectroscopy (DLTS) implemented on two InP samples annealed with identical effective thermal budgets, shows an additional electron trap when RTA is performed in the graphite cell. The latter mode was optimized for a plateau duration of about 10 s at 750 °C as confirmed by capacitance–voltage (C–V) measurements.