Study of trap centres in silicon nanocrystal memories

This work reports on a comprehensive study of trapping centres in Si nanocrystal based memories. Silicon nanotrap memories have been studied using static, transient and low frequency techniques in the 80–400 K temperature range. Fast traps at the SiO2/substrate interface have been characterised by I–V–T and charge pumping (CP) techniques and we have shown that the density of fast traps drastically increases below 150 K from a few 1010 cm−2 eV−1 up to a few 1011 cm−2 eV−1. DLTS experiments have shown that the fast interfacial traps are mainly located at Ec −0.26 eV with a capture cross section of 2.1×10−15 cm2. The spectroscopic study of nc-Si has been performed on thin tunnel oxides from 0.8 to 2.0 nm. We have been able to discriminate slow traps and fast traps with temperatures above 300 K with the CP technique which allows measurements from 10 Hz to 1 MHz. Using DLTS, we have been able to observe tunnel emission from nc-Si around 250 K for emission rate windows of 2.3 and 4.6 Hz. At room temperature, we show that the stored electrons in the memory are not only located on the nanocrystals. The interface traps between the deposited high temperature oxide (HTO) and the thermal oxide are shown to play a significant role. The trapping mechanisms on nc-Si seems to be related both to the nc-Si surface at low T and to the quantum levels at high T. We have shown that above 350 K, most of the trapping mechanisms are due to the Si quantum dots.