A novel technique for fabricating trench MOSFET employing oxide spacers and self-align techniques

A new process technique for fabricating very high-density trench MOSFETs using three mask layers with oxide spacers and self-align technique is realized. This technique reduces the process steps, trench width, and source and p-body region with a resulting increase in cell density and current driving capability, and decrease in on-resistance as well as cost-effective production capability. The channel density of the trench DMOSFET with a cell pitch of 2.3–2.4 μm is 110 Mcell per in.2 and the specific on-resistance of 0.41 mΩ·cm2 is obtained under the blocking voltage of 43 V.