Electrical properties of metal–oxide–silicon structures with LaAlO3 as gate oxide

In this paper, electrical investigations performed on complex metal–oxide–semiconductor (MOS) structures with amorphous LaAlO3 deposited as gate oxide on a rapid thermal processed SiO2 buffer layer are presented. Current–voltage (I–V) measurements at different temperatures and high frequency room-temperature capacitance–voltage (C–V) measurements indicate the presence of a non-equilibrium state in p-type Si (1 0 0) substrate under reverse polarization of the structure. The asymmetry in I–V characteristics is opposite to the expected one for the high-κ/interfacial layer stack behavior. Different indications for the non-equilibrium MOS state are inferred from the experimental data, and the extraction of MOS physical parameters by using the classical C–V method is shown to be unreliable. For small and large applied forward voltages defect-related charge transport and tunneling currents dominate, respectively.