Sub-50 nm gate length SOI transistor development for high performance microprocessors

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (LGATE) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and LGATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI.