Improved CMOS performance via enhanced carrier mobility

The amazing advancements achieved to date in Si complementary metal-oxide-silicon (CMOS) technology have come primarily from scaling, i.e. from reducing the critical dimensions of the transistors. Now that it is increasingly difficult to further reduce critical dimensions, alternative methods of improving transistor performance are also being employed. One important approach is to increase the electron and hole mobility in the transistors. Various approaches for achieving enhanced mobility in CMOS devices are reviewed. Methods for achieving defect-free strained Si structures are discussed.