Simulation of the sub-melt laser anneal process in 45 CMOS technology—Application to the thermal pattern effects

Due to the continuous CMOS transistor scaling requirements, sub-melt millisecond laser annealing has been introduced in 45 nm CMOS technology to enhance dopant activation without any additional diffusion. Because of the design, the device layout at the wafer surface introduces during this process significant variations of optical absorption and heat transfer that can induce temperature non-uniformities over the die, detrimental to the device and often called “pattern effects”. The introduction of an absorbent layer above the wafer reduces the optical properties dispersion, but the temperature variations generated by the thermal properties non-homogeneities cannot be suppressed. The impossibility to measure directly this local transient temperature effects on complex transistors layout requires simulation. A thermal simulation has been developed and calibrated to model with accuracy the laser annealing with the real process parameters. This model is used to obtain the transient temperature distribution over the devices, which is needed to understand the laser impact on the transistors performance. We demonstrate that the shallow trench isolation (STI) filled with silicon oxide is critical for these thermal pattern effects. Depending on the STI layout density, temperature variations up to 50 °C over a die are observed.