Performances of a multichannel 1 GHz TDC ASIC for the KLOE Tracking Chamber

The KLOE TDC is a multichannel common start/stop time-to-digital converter, with 32 channels per chip. The time measurement is done digitally by counting 1 GHz clock periods generated by an internal Delay Locked Loop (DLL). The circuit has a 500 ps resolution over a programmable time window of up to 65 μs, and is capable of recording up to 16 rising or falling edges per channel. It has a double-edge resolution of 5 ns and is capable of resolving a pulse of 3 ns width. The experiment requires that the data read out does not introduce dead time on top of the 2 μs digitization time of the calorimeter electronics. A multievent architecture has been implemented to satisfy this requirement. The experimental DAQ chain can read framed and zero suppressed data from the internal buffers at a maximum data throughput of 720 Mbit/s while the ASIC is recording new events. The chip has been realized as a full-custom device in 0.5 μm CMOS technology, it has been fully tested both in the laboratory and on a test beam, all the specifications are met. l of 15 000 channels are being produced for the KLOE experiment.