Data read out and formatting for PMT-based rich detectors

A compact Data Read Out System has been developed for PMT-Based Rich to perform the charge conversion, pixel encoding and data formatting for a large number of channels. This system is principally built around three circuits: A full custom VLSI circuit (ASIC) for charge conversion, a Field Programmable Gate Array (FPGA) for pixel encoding, thresholds and 12-bit ADC control, and a fast Digital Signal Processor (DSP) for data formatting.