Title of article
Front-end readout system for PHENIX RICH
Author/Authors
Tanaka، نويسنده , , Y and Hara، نويسنده , , H and Ebisu، نويسنده , , K and Hibino، نويسنده , , M and Kametani، نويسنده , , S and Kikuchi، نويسنده , , J and Wintenberg، نويسنده , , A.L and Walker، نويسنده , , J.W and Franck، نويسنده , , S and Moscone، نويسنده , , C and Jones، نويسنده , , J.P. and Young، نويسنده , , G.R and Matsumoto، نويسنده , , T and Sakaguchi، نويسنده , , T and Oyama، نويسنده , , K and Hamagaki، نويسنده , , H، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2000
Pages
13
From page
576
To page
588
Abstract
A front-end readout system with a custom backplane and custom circuit modules has been developed for the RICH subsystem of the PHENIX experiment. The design specifications and test results of the backplane and the modules are presented in this paper. In the module design, flexibility for modification is maximized through the use of Complex Programmable Logic Devices. In the backplane design, a source-synchronous bus architecture is adopted for the data and control bus. The transfer speed of the backplane has reached 640 Mbyte/s with a 128-bit data bus. Total transaction time is estimated to be less than 30 μs per event when this system is used in the experiment. This result indicates that the performance satisfies the data-rate requirement of the PHENIX experiment.
Keywords
ELECTRONICS , rich , CPLD , backplane , Source-synchronous
Journal title
Nuclear Instruments and Methods in Physics Research Section A
Serial Year
2000
Journal title
Nuclear Instruments and Methods in Physics Research Section A
Record number
2188160
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