Trigger processing using reconfigurable logic in the CMS calorimeter trigger

We present the design of the Global Calorimeter Trigger processor for the CMS detector at LHC. This is a fully pipelined processor system which collects data from all the CMS calorimeters and produces summary information used in forming the Level-1 trigger decision for each event. The design in based on the use of state-of-the-art reconfigurable logic devices (FPGAs) and fast data links. We present the results of device testing using a low-latency pipelined sort algorithm, which demonstrate that an FPGA can be used to perform processing previously foreseen to require custom ASICs. Our design approach results in a powerful, flexible and compact processor system.