Temperature characterization of deep and shallow defect centers of low noise silicon JFETs

We have selected different low noise JFET processes that have shown outstanding dynamic and noise performance at both room temperature and low temperatures. We have studied JFETs made with a process optimized for cryogenic operation, testing several devices of varying capacitance. For most of them, we have been able to detect the presence of shallow individual traps at low temperature which create low frequency (LF) Generation–Recombination (G–R) noise. For one device type no evidence of traps has been observed at the optimum temperature of operation (around 100 K). It had a very small residual LF noise. This device has been cooled down to 14 K. From below 100 K down to 14 K the noise was observed to increase due to G–R noise originating from donor atoms (dopants) inside the channel. A very simple theoretical interpretation confirms the nature of G–R noise from these very shallow trapping centers. We also studied devices from a process optimized for room temperature operation and found noise corresponding to the presence of a single deep level trap. Even for this circumstance the theory was experimentally confirmed. The measurement approach we used allowed us to achieve a very high accuracy in the modeling of the measured G–R noise. The ratio of the density of the atoms responsible for G–R noise above the doping concentration, NT/Nd, has been verified with a sensitivity around 10−7.