Analysis and simulation of charge collection efficiency in silicon thin detectors

Thin detectors have been proposed to investigate the possibility to limit the full depletion voltage and the leakage current of heavily irradiated silicon devices. In this work we compare typical silicon detectors (p–n junctions over a 300 μm thick substrate) with thinned devices (50–100 μm of thickness). In order to investigate the performances of these structures, simulations have been carried out using the ISE-TCAD DESSIS device simulator. The so called three-level model has been used to investigate the effects of the radiation fluence on charge collection efficiency of thin and thick silicon structures. For each thickness, we simulate the hit of a minimum ionizing particle and then we calculate the current at the diodeʹs electrode. We consider a 7×1011 cm−3 n-doped substrate (a high resistivity substrate); all the structures are composed of a 40 μm diode contact and a 15 μm distant guard ring. The simulated collected charge of the 300 μm diode is in agreement with the experimental results; the simulation of thinner structures (50–100 μm) shows a saturation of the number of e–h pairs collected at the diodeʹs electrodes. These results suggest that thin detectors may have a better performance at higher fluences than thick ones. They are maximizing the collected charge at lower depletion voltage.