Author/Authors :
Aslanides، نويسنده , , E. and Cachemiche، نويسنده , , J.-P. and Cogan، نويسنده , , J. and Dinkespiler، نويسنده , , B. and Favard، نويسنده , , S. and Duval، نويسنده , , P.-Y. and Le Gac، نويسنده , , Wayne R. and LeRoy، نويسنده , , O. and Liotard، نويسنده , , P.-L. and Marin، نويسنده , , F. and Menouni، نويسنده , , M. and Roche، نويسنده , , A. and Tsaregorodtsev، نويسنده , , A.، نويسنده ,
Abstract :
A very compact architecture has been developed for the first level muon trigger of the LHCb experiment that processes 40 × 10 6 proton–proton collisions per second. For each collision, it receives 3.2 kBytes of data and it finds straight tracks within a 1.2 μ s latency. The trigger implementation is massively parallel, pipelined and fully synchronous with the LHC clock. It relies on 248 high density Field Programable Gate Arrays and on the massive use of multigigabit serial link transceivers embedded inside FPGAs.
Keywords :
High speed serial link , First level trigger , Muon detector , LHCB , High density FPGA
