Author/Authors :
Barbero، نويسنده , , M. and Arutinov، نويسنده , , D. and Beccherle، نويسنده , , R. and Darbo، نويسنده , , G. and Ely، نويسنده , , R. and Fougeron، نويسنده , , D. and Garcia-Sciveres، نويسنده , , M. and Gnani، نويسنده , , D. and Hemperek، نويسنده , , T. and Karagounis، نويسنده , , M. and Kluit، نويسنده , , R. and Kostioukhine، نويسنده , , V. and Mekkaoui، نويسنده , , A. and Menouni، نويسنده , , M. and Schipper، نويسنده , , J.-D.، نويسنده ,
Abstract :
A new pixel Front-End (FE) IC is being developed in a 130 nm technology for use in the upgraded ATLAS pixel detector. The new pixel FE will be made of smaller pixels (50×250 μm vs. 50×400 μm for the present FE, FE-I3), a much improved active area over inactive area ratio, and a new analog pixel chain tuned for low power and new detector input capacitance. The higher luminosity for which this IC is tuned implies a complete redefinition of the digital architecture logic, which will not be based on End-of-Column data buffering but on local pixel logic and local pixel data storage. An overview of the new FE is given with particular emphasis on the new digital logic architecture and possible architecture variations.
Keywords :
pixel , FE-14 , Super-LHC , Digital architecture
