Title of article :
Control and data acquisition ATCA/AXIe board designed for high system availability and reliability of nuclear fusion experiments
Author/Authors :
Batista، نويسنده , , A.J.N. and Leong، نويسنده , , C. and Bexiga، نويسنده , , V. and Rodrigues، نويسنده , , A.P. and Combo، نويسنده , , A. and Carvalho، نويسنده , , B.B. and Carvalho، نويسنده , , P.F. and Fortunato، نويسنده , , J. and Santos، نويسنده , , B. and Carvalho، نويسنده , , P. and Correia، نويسنده , , M. and Teixeira، نويسنده , , J.P. and Teixeira، نويسنده , , I.C. and Sousa، نويسنده , , J. and Gonçalves، نويسنده , , B. and Varandas، نويسنده , , C.A.F.، نويسنده ,
Issue Information :
روزنامه با شماره پیاپی سال 2013
Abstract :
This paper describes the implementation and test of a control and data acquisition board designed to be integrated on systems demanding high availability and reliability, foreseen for future experiments like ITER or other long operation fusion devices. The Advanced Telecommunications Computing Architecture (ATCA) standard (PICMG 3.0 and 3.4) was selected for board implementation, which has support for the desired system robustness and performance. Some board features such as rear Input/Output (IO) signals connectivity (passive, copper tracks only), cable-less hot-swap maintenance, Intelligent Platform Management Controller (IPMC) and redundancy on timing signals, communications links and power supplies are significant board improvements, relatively to previous control and data acquisition boards, allowing the development of more reliable system architectures. Moreover, the developed board is also compatible with the emerging ATCA eXtensions for Instrumentation (AXIe) specifications, which provides additional timing and synchronization signals on the backplane. ATCA full-mesh, multi-gigabit, full-duplex, point-to-point communication links between Field Programmable Gate Arrays (FPGA), of peer boards inside the shelf, allow the implementation of distributed algorithms and development of Multi-Input Multi-Output (MIMO) systems. Up to 48 analog input channels, simultaneously digitized (2 MSPS @ 18-bits), are filtered/decimated by the board FPGA and sent to the ATCA/AXIe host through Peripheral Component Interconnect express (PCIe) using Direct Memory Access (DMA). In real-time, the host can update up to 48 analog output channels (1 MSPS @ 18-bits), per board, through PCIe. Further board characteristics comprise analog IO channels with galvanic isolation and an optional signal chopper mode, for offset compensation over time on digital integration of magnetic signals. Board time synchronization is attained by means of the Inter-Range Instrumentation Group (IRIG) time-code.
Keywords :
Fast control , DATA ACQUISITION , PCI Express , ATCA , AXIe , FPGA
Journal title :
Fusion Engineering and Design
Journal title :
Fusion Engineering and Design