Author/Authors :
Jalalifar, M. Department of Electrical Engineering - K.N Toosi University of Technology - Tehran, Iran , Yavari, M. Department of Electrical Engineering - K.N Toosi University of Technology - Tehran, Iran , Raissi, F. Department of Electrical Engineering - K.N Toosi University of Technology - Tehran, Iran
Abstract :
This paper presents a dual-active capacitance in reversed nested Miller compensation (DACRNMC) technique for
low-voltage and large capacitive load amplifiers. The frequency bandwidth of the DACRNMC amplifier has been
improved due to the usage of active compensation capacitors. The amplifier's die area is reduced in compare to the
existing techniques in the RNMC scheme. The architecture also generates two left half plane zeros to increase the
phase margin. The simulation for the proposed DACRNMC amplifier with a 0.18μm standard CMOS process reveals
a unity gain bandwidth of 17.4MHz and phase margin of 64 degrees , while 500 pF load is driven from a single 1.5 V
power supply.
