FPGA Placement Optimization using Firefly Algorithm

Field Programmable Gate Array (FPGA) technology has been surging in popularity across all industries. Digital circuit design using FPGA provides many benefits over previous methods like ASIC implementation. However, the fixed hardware structure of FPGA demands an efficient placement and routing technique for high-performance goals. It has already been demonstrated that metaheuristic algorithms like Particle Swarm Optimization (PSO) can successfully optimize circuit designs for the FPGA placement and routing problem. The limitation of PSO lies in the explosion of particle swarms due to unbounded exploration. This paper proposes the application of Firefly Algorithm (FA) as an alternative and competitive metaheuristic solution for FPGA placement optimization. The design optimization of a single BCD counter circuit is performed by applying the proposed algorithm on Xilinx software generated netlist and the simulation result is compared with the existing PSO based placement techniques aiming at better placement optimization and utilization of FPGA resources.