Multiple-Fault Tolerant Hardware Structure for Cellular Genetic Algorithm

This paper presents the hardware simulation (based on VHDL code) of a multiple-fault tolerant cellular genetic algorithm. This study aims to increase the immunity of cellular genetic algorithm in a multiple-fault situation. Here, multiple-fault refers to the situation that SEU (single event upset) occurs simultaneously at two or more bits of the chromosome and tness registers. The fault model includes simultaneous bit inversion in chromosome strings and the worst case stuck faults in tness registers. The main idea of the proposed approach is to control the trade-off between exploration and exploitation in fault recovery phase. The achievements of this experiment are novel recovery strategy due to applying CRC encoding and a new scheme in connections of processing elements. In order to show valid results, the algorithm is tested with four benchmarks in various fault situations based on popular evaluation metrics. In experimental results, two topologies (two and three-dimensional) of suggested MFT-cGA are evaluated. To illustrate the achieved immunity and improvement, the proposed MFT-cGA is compared with the canonical version of cGA. The whole results show that the proposed architecture is able to handle multiple-faults with up to 100% of faulty processing elements.