Design and Implementation of Field Programmable Gate Array Based Baseband Processor for Passive Radio Frequency Identification Tag

In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is compatible with the EPC C C2/ISO18000-6B protocol. Several design approaches such as clock gating technique, clock strobe design and clock management are used. In order to reduce the area Decimal Matrix Code (DMC) technique is used. The digital base band processor has been simulated and implemented using Xilinx platform. The complete design is verified and tested on Spartan-6 Field Programmable Gate Array (FPGA) board. The performance of system is measured in terms of power. The synthesis result shows that, the power required for complete design of digital baseband processor is 5mW on a supply voltage of 1.2 V.