Title of article :
NodeFetch: High Performance Graph Processing Using Processing in Memory
Author/Authors :
Mosayebi, M.A. Department of Computer Systems Architecture - Faculty of Computer Engineering - K. N. Toosi University of Technology - Tehran - Iran , Dehyadegari, M. Department of Computer Systems Architecture - Faculty of Computer Engineering - K. N. Toosi University of Technology - Tehran - Iran
Abstract :
Background and Objectives: Graph processing is increasingly gaining
attention during era of big data. However graph processing applications are
highly memory intensive due to nature of graphs. Processing-in-memory
(PIM) is an old idea which revisited recently with the advent of technology
specifically the ability to manufacture 3D stacked chipsets. PIM puts forward
to enrich memory units with computational capabilities to reduce the cost of
data movement between processor and memory system.
This approach seems to be a way of dealing with large-scale graph
processing, considering recent advances in the field.
Methods: This paper explores real-world PIM technology to improve graph
processing efficiency by reducing irregular access patterns and improving
temporal locality using HMC.
We propose NodeFetch, a new method to access nodes and their neighbors
while processing a graph by adding a new command to HMC system.
Results: Results of our simulation on a set of real-world graphs point out that
the proposed idea can achieve 3.3x speed up in average and 69% reduction
of energy consumption over the baseline PIM architecture which is HMC.
Conclusion: Most of the techniques in the field of processing-in-memory,
hire methods to reduce movement of data between processor and memory.
This paper proposes a method to reduce graph processing execution time
and energy consumption by reducing cache misses while processing a graph
Keywords :
Graph processing , Hybrid Memory Cube (HMC) , Processing in memory , Hardware Accelerator
Journal title :
Journal of Electrical and Computer Engineering Innovations (JECEI)