A New Tri-State Based Static Random Access Memory with Improved Write-Ability and Read Stability

In this paper, we have presented a new design for Static Random Access Memory Cell. In our first improvement, we add one PMOS and one NMOS transistor to conventional 6T SRAM cell leading to 8T cell. In this way, we improve the performance of cell. However, we reduce the overhead of area by sharing the added two transistors among four cells in the same row of an SRAM array, so we obtain an equivalent 6.5T cell. These extra transistors help to improve write-ability by breaking the feedback of back to back inverters during write operation. By mean of this innovation, we obtained improvement in Write Noise Margin (WNM) by 60% over conventional 6T cell which approves efficiency of our approach. Proposed 8T SRAM cell also reduces leakage power and active power for single write operations by 15% and 54% over 6T design at supply voltage of 500mV. To consider further scaling, proposed 8T SRAM cell is redesigned using 16nm PTM Bulk-CMOS and Fin FET transistors. Simulations with this condition show considerable improvement in Read Static Noise Margin (RSNM) and Hold SNM (HSNM) for Fin FET-based-cell. Finally, a 32kb SRAM using the proposed scheme is designed in a 90nm industrial CMOS technology. Detailed simulations also predict that at supply voltage of 800mV, read and write powers per operation of our design will be 0.36pJ and 7.5pJ, respectively and it is operational at frequencies as high as 1.43GHz.