Dual phase detector based on delay locked loop for high speed applications

In this paper a new architecture for delay locked loops is proposed. Static phase offset and reset path delay are the most important problems in phase-frequency detectors (PFD). The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and output of the DLL. Near locking, an XOR gate is used to act as a PFD which makes the DLL locks with less jitter. Also, the reset path time and glitch are decreased by using the XOR gate. The proposed architecture has been designed in TSMC 0.18um CMOS Technology. The simulation results support the theoretical design aspects.