Curent-Voltage Analysis of Nanoscale Planar and Vertical MOSFET Incorporating Dielectric Pocket

Characterization of nanoscale planar and vertical metal-oxide-semiconductor field effect transistor incorporating dielectric pocket (DP-MOSFET) is demonstrated by using numerical simulation. Vertical MOSFET is one solution to shrink the channel length (Lg) into nanometer regime. The comparison between planar and vertical MOSFET was done to show an advantages of dielectric pocket and each performances in current-voltage analysis. Dielectric pocket is incorporated between the channel and source/drain for suppression of short-channel effects (SCE) and bulk punch- through. The current-voltage analysis for both structure shows rational value of threshold voltage (VT), drive current (ION), off-state leakage current (IOFF), subthreshold swing (S) and Drain Induced Barrier Lowering (DIBL). A better control of VT roll-off was also demonstrated by incorporation of DP and better for vertical MOSFET compared to planar MOSFET. Thus, the incorporation of DP will enhance the electrical performance and give a very good control of the SCE for scaling the MOSFET in nanometer regime for future development of nanoelectronics product.